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Date: Fri, 31 Jan 1997 02:12:15 +0900
From: KATO Takenori <kato@eclogite.eps.nagoya-u.ac.jp>
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Subject: [FreeBSD-tech-jp 51] [BETA Version] CPU initialization routine
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Once one of the following CPUs is detected, initialization routine
configure the register or registers to enable or disable specific
feature of each CPU.

	Cyrix	486 series		CPUCLASS_486
	Cyrix	5x86 (M1sc)		CPUCLASS_486
	Cyrix	6x86 (M1)		CPUCLASS_486	(1)
	IBM	Blue Lightning CPU	CPUCLASS_486

Note 1: Cyrix 6x86 supports the 486 instruction set.  Pentium extensions
        are not supported.


The following kernel configuration time options are available:

IBM Bluelightning CPU:

	options	BLUELIGHTNING_WITH_INTEL_FPU
	    If you use Bluelightning CPU with Intel FPU, you should
	    add this option.  If you use Cyrix FPU, don't need to add
	    this option.


Cyrix 486 CPUs:

	options	CYRIX_CACHE_WORKS
	    This option enables CPU cache in hold-state flush mode.

	options	CYRIX_CACHE_READY_WORKS
	    This option enables CPU cache.


Cyrix 5x86 CPU:

	options	SUSP_HLT
	    If this option is set, CPU enters power save mode
	    following HALT instruction.

	options	"FASTER_5X86_FPU"
	    This option enables fast FPU exception handler.  If this
	    option is set, FPU instruction becomes faster, but kernel
	    cannot handle FPU exception.  I have not yet implemented
	    "FPU_ERROR_BROKEN" option on !pc98 tree.

	options "CYRIX_IORT=0"
	    This option tells I/O recovery time. (1)

	options	RSTK_EN
	    This option enables return stack. (2)

	options	BTB_EN
	    This option enables branch target buffer. (2)

	options	LOOP_EN
	    This option enables loop optimization. (2)

	options "DISABLE_5X86_LSSER"
	    This option enables reordering of memory access. (3)


Cyrix 6x86 CPU (4):

	options	SUSP_HLT
	    If this option is set, CPU enters power save mode
	    following HALT instruction.

	options "CYRIX_IORT=7"
	    This option tells I/O recovery time. (5)

	options CYRIX_REALLY_WORKS
	    If revision number is 2.6 or lower, CPU cache is enabled
	    in write-through mode.  If revsion number is higher than
	    2.6 or CYRIX_REALLY_WORKS is defined, CPU cache is enabled 
	    in write-back mode. (6)


i486 based CPU upgrade product for i386 machines:

	options "I486_ON_386"
	    This option enables CPU cache.


CPU upgrade product with cache control hardware (PC-98 only):

	options UPGRADE_CPU_HW_CACHE
	    This option eliminate extra invaldating of CPU cache. (7)


Note 1:	Default is 0 (no clock delay).  If you set other value,
	kernel could be crashed because of CPU bug.
Note 2: These options could crash a system because of CPU bug.
Note 3: If you use memory mapped I/O device(s), don't use this
	option.
Note 4:	Don't be suprised at 486-class CPU, please.  Cyrix 6x86
	supports the 486 instruction set.  Pentium extensions for
	virtual mode and internal timer are not supported.
Note 5: Default is 7, which is recomended value in "Cyrix 6x86 BIOS
	Writers Guide".
Note 6:	Write-back cache could crash your system with earlier version
	of 6x86.
Note 7: I think this option is not needed by IBM-PC users.


----
KATO Takenori <kato@eclogite.eps.nagoya-u.ac.jp>
Dept. Earth Planet. Sci., Nagoya Univ.,  Nagoya, 464-01, Japan
PGP public key: finger kato@eclogite.eps.nagoya-u.ac.jp
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